software, either directly or indirectly. The dotted lines show where I C-specific interrupt flags are set
Figure 15.10. I C Master State Machine
...the world's most energy friendly microcontrollers
After the address has been transmitted, a sequence of bytes can be read from or written to the slave,
depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master
has entered a master transmitter role, where it now transmits data to the slave. If the bit was set, it
has entered a master receiver role, where it now should receive data from the slave. In either case, an
unlimited number of bytes can be transferred in one direction during the transmission.
At the end of the transmission, the master either transmits a repeated START condition (Sr) if it wishes
to continue with another transfer, or transmits a STOP condition (P) if it wishes to release the bus.
15.3.7.1 Master State Machine
The master state machine is shown in Figure 15.10 (p. 151) . A master operation starts in the far
left of the state machine, and follows the solid lines through the state machine, ending the operation or
continuing with a new operation when arriving at the right side of the state machine.
Branches in the path through the state machine are the results of bus events and choices made by
2
along the path and the full-drawn circles show places where interaction may be required by software
to let the transmission proceed.
2
Master transm itter
0/1
57
97
D7
Idle/busy
Waiting
for idle
S
ADDR W
A
DATA
A
P
0
Bus state/event
9F
N
DF
Sr
57
Transm itted by self
N
Received from slave
Arb. lost
1
S
START
condition
P
STOP
condition
Master receiver
Sr
Repeated START condition
ADDR R
A
93
DATA
B3
A
P
0
A
ACK
N
NACK
Sr
57
ADDR W
ADDR R
Slave address + write
(R/W bit cleared)
Slave address + read
(R/W bit set)
Bus state (STATE)
N
9B
N
X
Arb. lost
1
Arbitration lost
Interrupt flag set
Interaction required. Wait-
ADDR R
Arb. lost, ADDR m atch
73
Slave transm itter
states inserted until m anual
or autom atic interaction has
been perform ed
Go to state
ADDR W
ADDR X
Arb. lost, ADDR m atch
Arb. lost, no m atch
71
1
Slave receiver
Bus reset
P
0
2011-04-12 - d0001_Rev1.10
151
www.energymicro.com
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